In a high speed synchronous semiconductor memory device such as a double data rate synchronous dynamic random access memory (DDR SDRAM), data is transferred (input from or output to) to other devices in synchronization with an external clock signal. That is, the high speed synchronous semiconductor memory device such as the DDR SDRAM performs an input or output operation in synchronization with not only a rising edge but also a falling edge of the external system clock signal. Typically, in a system or a circuit including a semiconductor memory, a clock signal is used as a reference signal for adjusting operation timing to guarantee stable data access and data transfer without error. For stable data access and data transfer, a delay occurring from the use of plural elements for data transfer should be compensated to exactly set a data output timing at edges of clock signal or on centers of clock signal.
To control the data output timing to be synchronized with the transition timing of the external clock, the synchronous semiconductor memory device includes a clock synchronization circuit. The clock synchronization circuit may include a phase locked loop (PLL) and/or a delay locked loop (DLL). Typically, in case that a frequency of the external clock differs from that of an internal clock in the semiconductor memory device, the PLL is used because the clock synchronization circuit can adjust the frequency of an internal clock in the semiconductor memory device. In case that a frequency of the external clock is the same as that of an internal clock in the semiconductor memory device, the DLL is generally used.
The delay locked loop generates a DLL output clock by compensating a clock skew occurring in a path having a predetermined delay amount estimated from a clock path and data path where data or the clock signal passes through in the semiconductor memory device; then, the DLL output clock is used for synchronizing data input/output with external clock. The DLL has better advantage for noise than the PLL used in a conventional device and, thus, is used broadly in the synchronous memory device including the DDR SDRAM. Recently, a register controlled DLL has been widely used. The register controlled DLL stores a prior delay amount for a delay locking state in a register when power is off, and when power is on, the register controlled DLL loads the stored delay amount for applying to a delay locking operation in order to reduce an initial time for the delay locking state.
As the semiconductor memory device operates faster, an input external clock and an internal clock can be distorted. If either the input external clock or the internal clock is distorted, the delay locked loop can generate faulty DLL clocks and, accordingly, the semiconductor memory device can operate abnormally due to the faulty DLL clocks. Further, if the input external clock and the internal clock are not distorted, the delay locked loop can distort DLL output clocks on operations for controlling a delay amount of the internal clock. In addition, correct duty ratio of the DLL output clocks is a critical factor for stable operations of the semiconductor memory device.
For maximizing a valid data window of outputting data in the semiconductor memory device, the internal clock used therein is symmetrically formed, i.e., it is required that the duty ratio of the internal clock should be 50:50. However, in the semiconductor memory device, the internal clock may not have a symmetrical waveform because an input clock is not symmetrical or the duty ratio is distorted by internal operations. For overcoming a distortion about the duty ratio of internal clock to set the duty ratio to 50:50, duty cycle compensation (DCC operation) is needed.
FIG. 1 is a block diagram of a conventional delay locked loop (DLL) performing duty cycle compensation.
As shown, the conventional delay locked loop (DLL) includes a clock buffer 10, first and second delay blocks 40 and 40′, first and second phase comparators 20 and 20′, first and second delay replica models 30 and 30′, a duty cycle compensation block, and first and second phase splitter. Herein, the duty cycle compensation block includes a DCC mixer 50, a dummy DCC mixer 60, a DCC phase comparator 80, and a mixer controller 70. The DCC mixer 50 is for mixing two clocks output from the first and second delay blocks 40 and 40′. The dummy DCC mixer 60 may be the same as the DCC mixer 50.
The clock buffer 10 receives an external clock signal CLK and an external clock bar signal CLKB to generate first and second internal clocks Clkin1 and Clkin2 and a reference clock Ref_clk.
The first and second delay comparators 20 and 20′ recognize a phase difference between input/output clocks of the delay locked loop. In detail, The first and second delay comparators 20 and 20′ respectively compare a phase of the reference clock Ref_clk output from the clock buffer 10 with those of first and second feedback clocks fb and fb2 output from the first and second delay replica models 30 and 30′ to thereby control the first and second delay blocks 40 and 40′ based on the comparison result.
The first and second delay blocks 40 and 40′ control delay amount of the first and second internal clocks Clkin1 and Clkin2 according to outputs of the first and second delay comparators 20 and 20′ respectively to generate first and second delay adjusted signals Rising_CLK and Falling_CLK.
The first and second delay replica models 30 and 30′ delay outputs of the duty cycle compensation block by a predetermined amount estimated from a clock path and data path where data or the clock signal passes through the semiconductor memory device. That is, the first and second delay replica models 30 and 30′ respectively include replica delay elements located in clock signal paths: one is from an input pin, i.e., inside of the chip, to the delay block 30, and the other is from the delay block 30 to an output pin.
The DCC mixer 50 is for mixing the first delay adjusted signals Rising_CLK output from the first delay block 40 for controlling a duty ratio to thereby set a 50:50 duty ratio.
Similar to the DCC mixer 50, the dummy DCC mixer 60, including the same elements as the DCC mixer 50, receives the second delay adjusted signals Rising_CLK output from the first delay block 40 to thereby set a 50:50 duty ratio.
The mixer controller 70 is for controlling the DCC mixer 50 and the dummy DCC mixer 60 in response to an output of the DCC phase comparator 80.
The DCC phase comparator 80 compares the first and second delay adjusted signals Rising_CLK output from the first delay block 40 with the second delay adjusted signals Falling_CLK output from the second delay block 40′ and determines a weight for the first and second delay adjusted signals Rising_CLK and Falling_CLK. Herein, the term “weight” means a value for increasing a size of an inverter, included DCC mixer 50 or the dummy DCC mixer 60′, coupled to one having a phase leading the other between the first and second delay adjusted signals Rising_CLK and Falling_CLK according to a comparison result of the DCC phase comparator 80.
The first and second phase splitters receive outputs of the duty cycle compensation block and outputs DLL clocks, e.g., rclkdll and fclkdll, to external circuits.
Hereinafter, operations of the conventional delay locked loop (DLL) performing duty cycle compensation are described.
Receiving the external clock signal CLK and the external clock bar signal CLKB, the clock buffer 10 generates the first and second internal clocks Clkin1 and Clkin2. The first and second internal clocks Clkin1 and Clkin2 are input to the first and second delay blocks 40 and 40′. Output from the first and second delay blocks 40 and 40′, the first and second delay adjusted signals Rising_CLK and Falling_CLK are input to the duty cycle compensation block; duty cycles of the first and second delay adjusted signals Rising_CLK and Falling_CLK are compensated. Thereafter, outputs of the duty cycle compensation block is fed back throughout the first and second delay replica models 30 and 30′ to output as the first and second feedback clocks fb and fb2. If rising edges of the first and second feedback clocks fb and fb2 correspond to that of the reference clock Ref_clk, the delay locked loop achieves a delay locking state.
Though the same clock can be input to the first and second delay blocks 40 and 40′, i.e., the first and second internal clocks Clkin1 and Clkin2 have the same phase, the second delay block 30′ generates an inverse signal of the input signal so that the first and second delay adjusted signals Rising_CLK and Falling_CLK have an opposite phase, i.e., duty ratios of the first and second delay adjusted signals Rising_CLK and Falling_CLK are opposite each other. Referring to FIG. 1, there is an inverter in the second delay block 40′ for inverting the duty ratio of the second delay adjusted signal Falling_CLK. For example, if the first delay block 40 includes two inverters at the end, the second delay block 40′ includes three inverters at the end.
On an initial operation, the DCC mixer 50 bypasses the first delay adjusted signal Rising_CLK in order to arrange the first feedback clock fb with the reference clock Ref_clk. Likewise, the dummy DCC mixer 60 also bypasses the second delay adjusted signal Fising_CLK so that the second feedback clock fb2 has the same delay as the first feedback fb; the output from the dummy DCC mixer 60 is passed throughout the second delay replica model 30′. Thereafter, If the second feedback fb2 is arranged with the reference clock Ref_clk, the delay locking state is achieved.
FIG. 2 is a schematic circuit diagram depicting a DCC mixer shown in FIG. 1.
As shown, the DCC mixer receives the first and second delay adjusted signals Rising_CLK and Falling_CLK to mix phases thereof in response to a mixing control signal mix, a weight selection signal weight_sel. Further, the DCC mixer is controlled by enable signals clkbuf_enb and DCC_enb for reducing power consumption. Also, power signals VSSDL and VDDL are used for adjusting a size of inverters between an internal node ‘a’ and the first and second delay adjusted signals Rising_CLK and Falling_CLK.
The DCC mixer is well known by people skilled in the art; thus, detailed description of the structure and operation of the DCC mixer is omitted herein.
FIG. 3 is a timing diagram demonstrating operations of the conventional delay locked loop (DLL) shown in FIG. 1.
As shown, after the delay locked loop achieves the delay locking state in two loops for the first and second internal clocks Clkin1 and Clkin2, the rising edge of the first delay adjusted signals Rising_CLK corresponds to that of the second delay adjusted signal Falling_CLK. However, duty ratios of the first and second delay adjusted signals Rising_CLK and Falling_CLK are opposite each other.
Thereafter, the DCC mixer 50 performs a phase mixing operation to the first and second delay adjusted signals Rising_CLK and Falling_CLK and, as a result, the delay locked loop can obtain a duty compensated clock mix_out having an exact 50:50 duty ratio. Based on the duty compensated clock, the first phase splitter generates the rising and falling DLL clocks rclkdll and fclkdll to external circuits.
As above described, on two loops in the delay locked loop the delay locking operation is independently performed; thus, a delay amount for the first internal clock Clkin1 to pass through one loop is different from the delay amount for second internal clock Clkin2 to pass through the other loop. For example, if a first internal clock Clkin1 having a 50% (50:50) duty ratio is locked without passing any delay element in one loop, the second internal clock Clkin2 should be passed through delay elements having ½ tCK delay time (1 tCK means one period of the external clock) for delay locking, i.e., corresponding to the rising edges of the first and second delay adjusted signals Rising_CLK and Falling_CLK.
It is assumed that a level of a power voltage VDD goes down. Even though the first and second delay adjusted signals Rising_CLK and Falling_CLK passes the same delay elements, a delay amount under a low power voltage is larger than that under a high power voltage. Accordingly, a phase difference between the first and second delay adjusted signals Rising_CLK and Falling_CLK become larger under the low power voltage.
FIG. 4 is a simulated waveform depicting a phase difference between the first and second delay adjusted signals according to decrease of a power voltage, and FIG. 5 is a waveform depicting distortion of the first and second delay adjusted signals according to variation of the power voltage.
Referring to FIGS. 5 and 6, there is a timing difference between rising edges of the first and second delay adjusted signals Rising_CLK and Falling_CLK according to increase or decrease of the power voltage. If the power voltage is varied after the delay locking state, there is a phase difference td between the first and second delay adjusted signals Rising_CLK and Falling_CLK. At this case, since the first and second delay blocks 40 and 40′ is operated based on the first and second feedback signals fb and fb2, the phase difference td cannot be removed.
FIG. 6 is a simulated waveform describing distortion of outputs from the DCC mixer 50 in response to the phase difference td between the first and second delay adjusted signals Rising_CLK and Falling_CLK shown in FIG. 1.
Referring to FIG. 6, if the phase difference td between the first and second delay adjusted signals Rising_CLK and Falling_CLK is ½ tCK, the rising and falling DLL clocks rclkdll and fclkdll are not toggled any longer. Accordingly, if the phase difference td between the first and second delay adjusted signals Rising_CLK and Falling_CLK is above a predetermined amount when the power voltage is varied after the delay locking state, the duty cycle compensation block cannot operate appropriately.